Systems Architect - Display Sub-System

Company: Qualcomm
Location: San Diego
Posted on: April 26, 2025

Job Description:

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Systems EngineeringGeneral Summary:Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry.Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products.Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following:

• Owning end to end system architecture
• Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification.
• Engage with all stakeholders and collaborate with cross functional teams to define robust architecture
• Defining architecture validation plans and reviewing development results
• Optimization and debug via modelling, system simulation and testing across key criteria including power and performance.
• Collaborating, reviewing and enabling design and system teams to execute independently from the specifications
• Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation
• Defining and patenting novel architectures that drive industry leadership.Job Function:
  • Oversees hardware architecture for ASIC systems development for a variety of products.
  • Determines architecture design, and validation via system simulation.
  • Defines module interfaces/formats for simulation.
  • Ability to analyze and solve complex problems through various mechanisms.
  • Ability to optimize architecture for Area, Performance and power efficiency.
  • Evaluates all aspects of the HW architecture flow from high-level development to validation and review.
  • Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results.
  • Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes.
  • Uses language such as HDL, C/C++, System C, Perl, Python.
    • Provides technical expertise for next generation initiatives.
    • Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques.
    • Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power.
    • Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met.
    • Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system.
    • Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems.
    • Writes technical documentation and provides technical expertise for design or project reviews and project meetings.
    • Acts as a tech lead on small to large projects and owns team deliverables of the project.Minimum Qualifications:Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Minimum Qualifications:Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience.ORMaster's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience.ORPhD in Science, Engineering, or related field.
      #J-18808-Ljbffr

Keywords: Qualcomm, Palm Springs , Systems Architect - Display Sub-System, Other , San Diego, California